Image processing apparatus and method of the same, and storage medium

ABSTRACT

A clock signal is frequency-modulated and an image processing operation is executed synchronously with the frequency-modulated clock signal to generate image data which is stored in a memory. Image data written in the memory is read synchronously with a clock signal having a fixed frequency. The image data written in the memory synchronously with the frequency-modulated clock signal is therefore converted into the image data synchronizing with the clock signal having a fixed frequency. Data subjected to image processing synchronously with the frequency-modulated clock signal can be output on the recording apparatus side without any practical problem.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to an image processing apparatusand an image processing method, and to a storing medium, and moreparticularly to an image processing apparatus and method suitable forapplication to a digital copier, a scanner or the like, and to a storingmedium.

[0003] 2. Related Background Art

[0004] An image processing apparatus such as a digital copier and ascanner is known, which reads an image of an original placed on anoriginal support and executes predetermined image processing. In aconventional image processing apparatus, a timing signal is generated inaccordance with a clock signal having a fixed frequency generated by aclock signal generation unit such as a quartz oscillator, andsynchronously with this timing signal, an original image is read togenerate image data which is subjected to various image processing.

[0005] With recent high speed and high resolution of sophisticated imageprocessing techniques, the frequency of a clock signal to be used forthe image processing by an image processing apparatus is becoming high.On the other hands, regulations on noises radiated from variouselectronic apparatuses are becoming sever one year after another. If theclock frequency is raised as in recent years, it is predicted thatcountermeasures against radiation noises of an image processingapparatus become more difficult. In order to meet the specifications ofelectromagnetic interference (EMI) adopted worldwide, it is necessary tosuppress the amount of radiation noises, which results in a smallerdegree of design freedom, a larger load upon a designer and a technicalperson, and a rise of manufacture cost.

[0006] As countermeasures against such radiation noises, there is amethod of modulating the frequency of a clock signal. However, if imagedata is processed by using a timing signal generated in accordance witha frequency-modulated clock signal, there occurs a problem that when theprocessed image data is output on a recording apparatus such as aprinter, the size of each dot becomes different. Furthermore, anabnormal operation, if any, of a frequency modulation function cannot benotified to a user.

SUMMARY OF THE INVENTION

[0007] It is an object of the present invention to output image dataprocessed synchronously with a frequency-modulated clock signal withoutany practical problem.

[0008] It is another object of the present invention to allow anoperator to confirm the operation state of a frequency modulationfunction.

[0009] According to embodiments of the present invention, the followingimage processing apparatus, image processing method, and storage mediumstoring program codes for realizing the image processing method areprovided.

[0010] An image processing apparatus comprises: a modulation circuit forfrequency-modulating a clock signal; a memory for storing image data; awrite circuit for writing image data in the memory, synchronously with afirst clock signal frequency-modulated by said modulation circuit; and aread circuit for reading image data from the memory, synchronously witha second clock signal having a fixed frequency.

[0011] An image processing apparatus comprises: an image reading unitfor reading an original image; an image processing circuit forsubjecting an image signal read with the image reading unit to apredetermined image processing operation; a first clock generationcircuit for generating a first clock signal to be used for processingthe image signal; a frequency modulation circuit forfrequency-modulating the first clock signal output from the first clockgeneration circuit; a first timing signal generation circuit forgenerating a first image processing timing signal in accordance with thefirst clock signal frequency-modulated by the frequency modulationcircuit; an image data generation circuit for processing the imagesignal synchronously with the first image processing timing signalgenerated by the first timing signal generator circuit to generate imagedata; a second clock generation circuit for generating a second clocksignal; a second timing signal generation circuit for generating asecond image processing timing signal in accordance with the secondclock signal output from the second clock generation circuit; a writecircuit for writing the image data generated by the image datageneration circuit in a memory, synchronously with the first timingsignal generated by the first timing signal generation circuit; a readcircuit for reading image data from the memory, synchronously with thesecond timing signal generated by the second timing signal generationcircuit; and an image processing circuit for processing the image dataread from the memory.

[0012] An image processing method comprises: a modulation step offrequency-modulating a clock signal; a write step of writing image datain a memory, synchronously with a first clock signal frequency-modulatedat said modulation step; and a read step of reading image data from thememory, synchronously with a second clock signal having a fixedfrequency.

[0013] An image processing method comprises: an image reading step ofreading an original image; an image processing step of subjecting animage signal read at the image reading step to a predetermined imageprocessing operation; a first clock generation step of generating afirst clock signal to be used for processing the image signal; afrequency modulation step of frequency-modulating the first clock signalgenerated at the first clock generation step; a first timing signalgeneration step of generating a first image processing timing signal inaccordance with the first clock signal frequency-modulated at thefrequency modulation step; an image data generation step of processingthe image signal synchronously with the first image processing timingsignal generated at the first timing signal generator step to generateimage data; a second clock generation step of generating a second clocksignal; a second timing signal generation step of generating a secondimage processing timing signal in accordance with the second clocksignal generated at the second clock generation step; a write step ofwriting the image data generated at the image data generation step in amemory, synchronously with the first timing signal generated at thefirst timing signal generation step; a read step of reading image datafrom the memory, synchronously with the second timing signal generatedat the second timing signal generation step; and an image processingstep of processing the image data read from the memory.

[0014] A storage medium storing a program for realizing an imageprocessing method, the method comprises: a modulation step offrequency-modulating a clock signal; a write step of writing image datain a memory, synchronously with a first clock signal frequency-modulatedat said modulation step; and a read step of reading image data from thememory, synchronously with a second clock signal having a fixedfrequency.

[0015] A storage medium storing a program for realizing an imageprocessing method, the method comprises: an image reading step ofreading an original image; an image processing step of subjecting animage signal read at the image reading step to a predetermined imageprocessing operation; a first clock generation step of generating afirst clock signal to be used for processing the image signal; afrequency modulation step of frequency-modulating the first clock signalgenerated at the first clock generation step; a first timing signalgeneration step of generating a first image processing timing signal inaccordance with the first clock signal frequency-modulated at thefrequency modulation step; an image data generation step of processingthe image signal synchronously with the first image processing timingsignal generated at the first timing signal generator step to generateimage data; a second clock generation step of generating a second clocksignal; a second timing signal generation step of generating a secondimage processing timing signal in accordance with the second clocksignal generated at the second clock generation step; a write step ofwriting the image data generated at the image data generation step in amemory, synchronously with the first timing signal generated at thefirst timing signal generation step; a read step of reading image datafrom the memory, synchronously with the second timing signal generatedat the second timing signal generation step; and an image processingstep of processing the image data read from the memory.

[0016] With the above embodiment structures, image data processedsynchronously with a frequency-modulated clock signal can be outputwithout any practical problem.

[0017] According to other embodiments of the invention, the followingimage processing apparatus and image processing method are provided.

[0018] An image processing apparatus comprises: a clock signalgeneration circuit for generating a clock signal; a frequency modulationcircuit for modulating a frequency of a generated clock signal; and adetection circuit for detecting an operation state of the frequencymodulation circuit.

[0019] An image processing method comprises: a clock signal generationstep of generating a clock signal; a frequency modulation step ofmodulating a frequency of a generated clock signal; and a detection stepof detecting an operation state of frequency modulation.

[0020] With the above embodiment structures, the operation state of afrequency modulation function can be confirmed.

[0021] Other objects and features of the present invention will becomeapparent from the following specification and the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022]FIG. 1 is a block diagram of an image processing apparatusaccording to an embodiment of the invention.

[0023]FIG. 2 is a graph illustrating the operation of a frequencymodulation unit of the apparatus shown in FIG. 1.

[0024]FIG. 3 is a frequency spectrum graph of the frequencies changingas shown in FIG. 2.

[0025]FIG. 4 is a circuit block diagram of a timing generation unit ofthe apparatus shown in FIG. 1.

[0026]FIG. 5 is a timing chart of signals generated by the timinggeneration unit of the apparatus shown in FIG. 1.

[0027]FIG. 6 is a circuit block diagram showing the structure of a CCDdrive timing signal generation unit of the apparatus shown in FIG. 1.

[0028]FIG. 7 is a timing chart of signals generated by the CCD drivetiming signal generation unit of the apparatus shown in FIG. 1.

[0029]FIG. 8 is a diagram showing signals supplied to an image memory.

[0030]FIG. 9 is a timing chart illustrating the operation of the imagememory of the apparatus shown in FIG. 1.

[0031]FIG. 10 is a flow chart illustrating an image processingoperation.

[0032]FIG. 11 is a block diagram showing the structure of an imageprocessing apparatus according to another embodiment.

[0033]FIG. 12 is a block diagram showing the image processing apparatusof the embodiment, mainly its image processing unit.

[0034]FIG. 13 is a circuit diagram of a frequency modulation stopdetection unit of the image processing apparatus shown in FIG. 11.

[0035]FIGS. 14A, 14B, 14C and 14D show the waveforms of signals at thefrequency modulation stop detection unit of the image processingapparatus shown in FIG. 11.

[0036]FIG. 15 is a flow chart illustrating a frequency modulation stopdetection operation to be executed by the image processing apparatusshown in FIG. 11.

[0037]FIG. 16 is a block diagram showing the structure of an imageprocessing apparatus according to another embodiment.

[0038]FIG. 17 is a block diagram showing the image processing apparatusof the embodiment, mainly its image processing unit.

[0039]FIG. 18 is a circuit diagram of a modulation width monitoring unitof the image processing apparatus shown in FIG. 16.

[0040]FIGS. 19A, 19B, 19C and 19D show the waveforms of signals at themodulation width monitoring unit of the image processing apparatus shownin FIG. 16.

[0041]FIG. 20 is a flow chart illustrating a modulation width monitoringoperation to be executed by the image processing apparatus shown in FIG.16.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0042] Embodiments of the invention will be described with reference tothe accompanying drawings.

[0043]FIG. 1 is a block diagram showing an example of an imageprocessing system according to an embodiment of the invention.

[0044] In FIG. 1, reference numeral 101 represents a first quartzoscillator which outputs a clock signal having a predeterminedfrequency.

[0045] An output of the first quartz oscillator 101 is supplied toa-frequency modulation unit 102. The frequency modulation unit 102frequency-modulates the input clock signal by a method, for example,disclosed in U.S. Pat. No. 5,488,627 and U.S. Pat. No. 5,631,920.

[0046] The clock signal frequency-modulated by the frequency modulationunit 102 is input to a CCD drive timing signal generation unit 103 forgenerating a drive signal for driving a CCD sensor 105 which reads animage, and for generating other timing signals.

[0047] The CCD drive signal generated by the CCD drive timing signalgeneration unit 103 includes a reset pulse signal RS for resettingcharges, a shift pulse signal SH for transferring charges to a shiftregister, a transfer clock signal φ for transferring changes in theshift register, and other signals. These signals RS, SH and 4 areboosted to necessary voltages and currents by the driver circuit 104 andsupplied to a CCD sensor 105.

[0048] An image signal output from the CCD sensor 105 is an analogsignal which is input to an amplifier circuit 106 to be amplified to asignal having an amplitude of, for example, 0 to 5 V. An output of theamplifier circuit 106 is input to an A/D converter to be converted intoa digital signal of, for example, 8 bits.

[0049] The CCD drive timing signal generator unit 103 also generates afirst image clock signal CLK1 which determines a sampling timing for A/Dconversion at the A/D converter 107. The image signal A/D converted bythe A/D converter 107 is temporarily stored in an image memory 108structured as a FIFO memory.

[0050] The CCD drive timing signal generator unit 103 also generatestiming signals necessary for data write into the image memory 108, thesignals including a first main scan sync signal HSYNC1, a first mainscan effective image section signal HE1 and a first image clock signalCLK1.

[0051] A timing signal generator circuit 109 generates timing signalsnecessary for data read from the image memory 108, synchronously with aclock signal generated by a second quartz oscillator 110, the timingsignals including a second main scan sync signal HSYNC2, a second mainscan effective image section signal HE2 and a second image clock signalCLK2.

[0052] The image signal read from the image memory 108 is firstsubjected to a variation correction in pixels of the CCD sensor 105 by ashading correction circuit 111, and thereafter subjected to amagnification process by a magnification circuit 112. In this case, foran image compression, a data thinning process is executed, whereas foran image enlargement, a data interpolating process is executed.

[0053] Next, a filter circuit 113 emphasizes edges of an image throughsecond order differentiation in a window of, for example, 5×5 pixels, orsmoothes the image. Since the image data is luminance data, the imagedata is converted, for example, into density data in order to print itout at a printer, by a gamma conversion circuit 114 by searching atable.

[0054] The image data converted into density data by the gammaconversion circuit 114 is then input to a binarization circuit 115whereat multi-value data is converted into binary data, for example, byan ED method. The image data binarized by the binarization circuit 115is input to a laser driver circuit 116.

[0055] Each image processing operation at the shading circuit 111,magnification circuit 112, filter circuit 113, gamma conversion circuit114 and binarization circuit 115 is controlled by the timing signals(second main scan sync signal HSYNC2, second main scan effective imagesection signals HE3 to HE7, and second image clock signal CLK2) allgenerated by the timing signal generation unit 109.

[0056] Next, the operation of the frequency modulation unit 102 will bedescribed with reference to FIGS. 2 and 3.

[0057] Consider first that the frequency of a clock signal generated bythe first quartz oscillator 101 is f0.

[0058]FIG. 2 is a characteristic diagram showing a change in thefrequency. In FIG. 2, the ordinate represents frequency and the abscissarepresents time. A change in the frequency of a clock signal output fromthe frequency modulation unit 102 is as in the following.

[0059] As shown in FIG. 2, the frequency changes with time in the orderof f0→f1→f2→f1→f0→f3→f4→f3→f0, where f4<f3<f0<f1<f2.

[0060] A ratio of the highest frequency f2 to the lowest frequency f4can be changed by the frequency modulation unit 102. For example, if amodulation width is set to f0±0.635%, then f2=1.00635*f0 and f4=0.99365*f0. This frequency modulation operation continues to be repeated.

[0061] The frequency spectra of the output clock signal are shown in thecharacteristic diagram of FIG. 3. The ordinate represents electric fieldintensity and the abscissa represents frequency. As shown in FIG. 3, ifthe frequency is fixed to f0, the spectrum waveform (indicated by adotted line) is a narrow waveform rising rapidly, whereas if thefrequency modulation is performed as shown in FIG. 2, the spectrumwaveform (indicated by a solid line) is a wide waveform extending fromthe frequency f4 to the frequency f2. The peak value of the electricfield intensity lowers by about 5 to 10 dB uV when the frequencymodulation is performed, so that the amount of noises to be externallyradiated can be reduced considerably.

[0062]FIG. 4 is a block diagram showing the internal structure of thetiming generation unit 109. Each image processing operation at theshading circuit 111, magnification circuit 112, filter circuit 113,gamma conversion circuit 114 and binarization circuit 115 is controlledby the timing signals (second main scan sync signal HSYNC2, second mainscan effective image section signals HE3 to HE7, and second image clocksignal CLK2) all generated by the timing signal generation unit 109.

[0063] The clock signal generated by the second quartz oscillator 110 isinput to a buffer 401. The clock signal output from the buffer 401 isinput to a counter 402 which counts the number of input clock signalsand outputs a count of, for example, a 14-bit width.

[0064] This count is input to a first input terminal A of a comparator403. Input to a second input terminal B of the comparator 403 is a valuelatched by a 14-bit register. This latched value determines the periodof the second main scan sync signal HSYNC2. When the count of thecounter 402 becomes coincident with the register value (when A=B), thecomparator 403 outputs a coincidence signal (“H” level) having one clockwidth.

[0065] The coincidence signal output from the comparator 403 is input toa D input terminal of a D-type flip-flop 404 and latched by the clocksignal output from the buffer 401. A negative logic output of thelatched coincidence signal becomes the second main scan sync signalHSYNC2. This signal is input to a CLR input terminal of the counter 402to clear the count thereof.

[0066] As shown in FIG. 5, the second main scan sync signal HSYNC2output from the flip-flop 404 has “L” levels of one pulse width with aperiod defined by the value of the register.

[0067] The clock signal output from the buffer 401 is also input toanother counter 405 which counts the number of input clock signals andoutputs a count of, for example, a 14-bit width.

[0068] This count is input to a first input terminal A of a comparator406. Input to a second input terminal B of the comparator 406 is a valuelatched by the 14-bit register. This value determines a start value ofthe main scan effective image section signal HE2. When the count of thecounter 405 becomes coincident with the value in the register, thecomparator 406 outputs a coincidence signal (“H” level) having one clockwidth.

[0069] The coincidence signal is input to a J input terminal of aJK-type flip-flop 408 and latched by the clock signal output from thebuffer 401. The count of the counter 405 is also input to a first inputterminal A of a comparator 407 and a value latched in the 14-bitregister is input to a second input terminal B of the comparator 407.

[0070] This value determines an end value of the main scan effectiveimage section signal HE2. When the count of the counter 405 becomescoincident with the value in the register, the comparator 407 outputs acoincidence signal (“H” level) having one clock width.

[0071] The coincidence signal is input to a K input terminal of theJK-type flip-flop 408 and latched by the clock signal supplied from thebutter 401. A negative logic output of the JK-type flip-flop 408 becomesthe second main scan effective image section signal HE2.

[0072] If the comparators 406 and 407 and JK-type flipflops 408 areprovided as many as the number of necessary main scan effective imagesection signals, each main scan effective image section signal can beoutput independently from each other. In this embodiment, signals HE2 toHE7 are generated. As shown in FIG. 5, each of the signals HE2 to HE7changes to the “L” level at the start register value, and to the “H”level at the end register value. The “L” level section is used as aneffective image area and each image processing circuit processes imagedata during this period.

[0073]FIG. 6 is a block diagram showing the internal structure of theCCD drive timing signal generation circuit 103.

[0074] As shown in FIG. 6, the modulated clock signal is input from thefrequency modulation unit 102 to the CCD drive timing signal generationcircuit 103. The input modulated clock signal is input to a firstfrequency divider 601 at which the frequency of the clock signal islowered to ½.

[0075] An output of the first frequency divider 601 is sequentially andserially input to second and third frequency dividers 602 and 603. Thefrequency of the output signal from the third frequency divider 603 is ⅛of that of the clock signal input to the first frequency divider 601.This output signal is used as the transfer clock signal φ fortransferring charges in the shift register.

[0076] The signal output from the third frequency divider 603 is inputto a clock input terminal of a D-type flip-flop 608. The second mainscan sync signal HSYNC2 is input to a D input terminal of the flip-flop608. A signal output from an inverted output terminal thereof is outputas the shift pulse signal SH to the driver circuit 104.

[0077] The signal output from the third frequency divider 603 is alsoinput to an inverter 604 to be inverted. The inverted signal determinesthe sampling timing for A/D conversion, and becomes the first imageclock signal CLK1 which is used as a write sync clock signal for theimage memory 108.

[0078] Each output from the first to third frequency dividers 601 to 603is input to a three-input AND gate 605. An output of the three-input ANDgate 605 is input to a D input terminal of a D-type flip-flop 607.

[0079] As a clock signal for latch timing of the flip-flop 607, themodulated clock signal input from the frequency modulation unit 102 andinverted by the inverter 606 is used.

[0080] The latch output of the flip-flop 607 is used as the reset pulseRS for resetting charges of CCD. The shift pulse signal SH fortransferring CCD charges to the shift register is a negative logicoutput of the first main scan sync signal HSYNC1 generated by the timingsignal generation unit 102 and latched by the D-type flip-flop 607 byusing the clock signal output from the frequency divider 603. The clocksignal output from the inverter 604 is input to a counter 609.

[0081] The counter 609 counts the number of input clocks and outputs acount having, for example, a 14-bit width. This count is input to afirst input terminal A of a comparator 610. A value latched in the14-bit register is input to a second input terminal B of the comparator610. This value determines a start value of, the first main scaneffective image section signal HE1. When the count of the counter 609becomes coincident with the register value, the comparator 610 outputs acoincidence signal (“H” level) having one clock width.

[0082] The coincidence signal is input to a J input terminal of aJK-type flip-flop 612 and latched by the clock signal output from theinverter 604. The count of the counter 609 is also input to a firstinput terminal A of a comparator 611.

[0083] A value latched in the 14-bit register is input to a second inputterminal B of the comparator 611. This value determines an end value ofthe first main scan effective image section signal HE1. When the countof the counter 609 becomes coincident with the register value, thecomparator 611 outputs a coincidence signal (“H” level) having one clockwidth.

[0084] The coincidence signal is input to a K input terminal of theJK-type flip-flop 612 and latched by the clock signal output from theinverter 604. A negative logic output of the JK-type flip-flop 612becomes the first main scan effective image section signal HE1. Thissignal is used as a write enable (WE) signal for the image memory 108 ofFIFO.

[0085] The second main scan sync signal HSYNC2 generated by the timingsignal generation unit 109 is input to a D-type flip-flop 613. An outputof the flip-flop latched by the clock signal output from the inverter604 becomes HSYNC1 which is used as a write reset (WRST) signal for theimage memory 108 of FIFO.

[0086] Each output signal generated by the CCD drive timing signalgeneration unit 103 is a signal modulated by a predetermined ratio,because the modulated clock signal from the frequency modulation unit102 is used as the input clock signal.

[0087]FIG. 7 is a timing chart of CCD drive signals and illustrates onemain scan operation.

[0088] During the “H” level period of the shift pulse signalsynchronizing with the main scan sync signal, CCD charges aretransferred to the shift register, and an output signal OS istransferred from CCD one pixel after another in response to the transferclock signal φ.

[0089] Since the transfer clock signal φ is frequency-modulated, itsperiod changes in the order of T1→T2→T3→T4 as shown in FIG. 7. The pixelreset pulse RS generated synchronously with the leading edge of thetransfer clock φ, CCD output signal OS, and A/D conversion samplingsignal also change their period similar to the transfer clock signal φ.

[0090] Therefore, the CCD output signal input to the A/D converter 107is sampled at the leading edges of the first image clock signal CLK1, sothat each pixel is always sampled at the center of one clock period. Inthe example shown in FIG. 7, ratios of A1:B1, A2:B2, A3:B3, and A4:B4are constant.

[0091] An A/D converted output is output synchronously with the leadingedge of the first image clock signal CLK1. Therefore, an image outputduring the T1 period of the transfer clock signal φ is D1 and has aperiod of T1′=B1+A2. Similarly, the image output during the period T2 isD2 and has a period of T2′=B2+A3.

[0092] In this embodiment, although the CCD drive signal isfrequency-modulated, image data at the same timing whenfrequency-modulation is not performed can be sampled.

[0093] Next, with reference to FIGS. 8 and 9, read timing of the imagememory 108 will be described.

[0094]FIG. 8 shows signals supplied to the image memory 108. This imagememory 108 is a FIFO memory capable of executing data read/writeasynchronously.

[0095] Signals necessary for data write include a write enable (WE)signal, a write reset (WRST) signal for resetting an internal addresscounter of the memory, and a write sync clock (WCK) signal. Signalsnecessary for data read includes a read enable (RE) signal, a read reset(RRST) signal for resetting an internal address counter of the memory,and a read sync clock (RCK) signal.

[0096] The signals necessary for data write are HE1, HSYNC1 and CLK1generated by the CCD drive timing signal generation unit 103. Thesignals necessary for data read are HE2, HSYNC2 and CLK2 generated bythe timing signal generation unit 109. Data to be input to the FIFOmemory 108 is data output from the A/D converter 107, and the read datais input to the shading correction circuit 111.

[0097]FIG. 9 is a timing chart showing timings of the above-describedmemory control signals. On the data write side, a write address counteris reset to “0” in response to the HSYNC1 signal.

[0098] Thereafter, when the HE1 signal takes the “L” level, the writeoperation starts. While the write address counter counts upsynchronously with the leading edge of the CLK1 signal, input data D1,D2, D3, D4, . . . is sequentially written. The memory control signalsare generated by the method described earlier and since the signal CLK1is frequency-modulated, the period of input data changes in the order ofT1′, T2′, T3′, T4′ . . . .

[0099] On the data read side, the read address counter is reset to “0”in response to the HSYNC2 signal. Thereafter, when the HE2 signal takesthe “L” level, the read operation starts. While the read address countercounts up synchronously with the leading edge of the CLK2 signal, datais sequentially read in the order of D1, D2, D3, D4 . . . . The memorycontrol signals are generated by the method described earlier and sincethe signal CLK2 has a fixed frequency, the period of read data is alwaysconstant.

[0100] With the read/write operation for the image memory 108 describedabove, data synchronizing with the frequency-modulated clock signal isconverted into data synchronizing with the clock signal having a fixedfrequency. In this embodiment, although the image memory 108 is insertedbetween the A/D converter 107 and shading correction circuit 111, theimage memory 108 may be inserted at any image processing position beforethe data output to the laser driver circuit 116.

[0101] In this case, the timing signal is generated synchronously withthe frequency-modulated clock signal until data is written in the imagememory 108, and thereafter the timing signal is generated synchronouslywith the clock signal having the fixed frequency.

[0102] Next, an example of the image processing method described abovewill be described with reference to the flow chart shown in FIG. 10. Asshown in FIG. 10, first at Step S1, a first clock signal for processingan image signal is generated.

[0103] Next at Step S2, the first clock signal generated at the clockgenerating step S1 is frequency-modulated.

[0104] Next at Step S3, in accordance with the first clock signalfrequency-modulated at the frequency modulation step S2, a first imageprocessing timing signal is generated.

[0105] Next at Step S4, synchronously with the first image processingtiming signal generated at the timing signal generation step S3, theimage signal is processed to generate image data.

[0106] Next at Step S5, a second clock signal is generated.

[0107] Next at Step S6, in accordance with the second clock signalgenerated at Step S5, a second image processing timing signal isgenerated.

[0108] Next at Step S7, image data is written in the image memory 108synchronously with the first timing signal generated at the first timingsignal generating Step.

[0109] Next at Step S8, the image data written in the image memory 108is read synchronously with the second timing signal generated at StepS6.

[0110] Next at Step S9, the image data read from the image memory 108 issubjected to predetermined image processing.

[0111] The read/write process for the image memory 108 may be executedat a desired image processing position before to the data output to thelaser driver circuit 116, as described previously.

[0112] As described so far, the clock signal synchronizing with imagedata is frequency-modulated and the image data is written in a memorysynchronously with the frequency-modulated clock signal, whereas theimage data written in the memory is read synchronously with the clocksignal having a fixed frequency without frequency modulation. It istherefore possible to convert the image data stored in the memorysynchronously with the frequency-modulated clock signal, into the imagedata synchronizing with the clock signal having a fixed frequency.Accordingly, the frequency of the clock signal can be modulated withoutthe problem that the size of each dot becomes different on the side of arecording apparatus such as a printer. Radiation noises of an imageprocessing apparatus can therefore be dealt with easily more than aconventional case.

[0113]FIG. 11 is a block diagram showing the structure of an imageprocessing apparatus according to another embodiment. The imageprocessing apparatus of this embodiment has a CPU 1101, a bus drivecircuit/address decoder circuit 1102, a read-only memory (ROM) 1103, amain memory (RAM) 1104, an I/O interface 1105, an operation panel 1106,a relay circuit 1107, a frequency modulation stop detection unit 1108, alaser unit 1109, a charge-coupled device (CCD) unit 1110, an imageprocessing unit 1111, and a video bus 1112.

[0114] The structure of each element will be detailed. CPU (centralprocessing unit) 1101 controls the entirety of the image processingapparatus, sequentially reads control programs from ROM 1103 to executethe processes illustrated in the flow chart of FIG. 15 and otherprocesses. The bus driver circuit/address decoder circuit 1102 connectsaddress and data buses of CPU 1101 to each load. ROM 1103 stores thereina control procedure (control programs) of the image processingapparatus. RAM (random access memory) 1104, which is a main memorydevice, is used as a storage area of input data or a working area ofdata. The I/O interface 1105 is connected to: the operation panel 1106;devices (not shown) including motors, clutches, solenoids for driving apaper feed system, a transport system and an optical system, and paperdetecting sensors for detecting a transported paper sheet; and torespective loads of the relay circuit 1107, frequency modulation stopdetection unit 1108 and laser unit 1109.

[0115] The operation panel 1106 includes various keys for entering databy an operator and a display unit such as a liquid crystal display andan LED for displaying the operation state and the like of the imageprocessing apparatus. The relay circuit 1107 turns on and off a power ofthe image processing circuit. The frequency modulation stop detectionunit 1108 detects a presence/absence of a frequency modulation stop (afailure of a frequency modulation unit 202 shown in FIG. 12) to bedescribed later. The CCD unit 1110 reads image data from an originalplaced on an original support and outputs it via the video bus 1112 tothe image processing unit 1111. The image processing unit 1111 performsimage processing to be described later for the image data output fromthe CCD unit 1110. The video bus 1112 connects the CCD unit 1110 to theimage processing unit 1111. The laser unit 1109 forms an image on asheet in accordance with image data supplied from the image processingunit 1111. The frequency modulation stop detection unit 1108 and CCDunit 1110 will be detailed with reference to FIG. 12.

[0116]FIG. 12 is a circuit block diagram of the image forming apparatus,mainly the image processing unit 1111 thereof. The image processing unit1111 of the image processing apparatus of this embodiment has a shadingcorrection circuit 1203, a magnification circuit 1204, an edge emphasiscircuit 1205, a gamma conversion circuit 1206, a binarization processingunit 1207, a synthesization circuit 1208, a memory control unit 1209, animage memory 1210, and a pulse width modulation (PWM) circuit 1211. InFIG. 12, reference numeral 1201 represents a quartz oscillator, andreference numeral 1202 represents a frequency modulation unit.

[0117] The structure and operation of each element will be detailed. Thequartz oscillator 1201 outputs a clock signal having a fixed frequency.The frequency modulation unit 1202 is input with the clock signalsupplied from the quartz oscillator 1201 and outputs a clock signalwhose frequency was modulated. This frequency modulation will be laterdetailed. The frequency modulation stop detection unit 1108 is inputwith the clock signal from the quartz oscillator 1201 and the clocksignal from the frequency modulation unit 1202, and outputs a modulationstop detection signal when the clock signal input from the frequencymodulation unit 1202 was not modulated.

[0118] The CCD unit 1110 is constituted of a focussing lens (not shown)for focussing light reflected from an original, an image pickup device(not shown) such as a CCD, a CCD driver (not shown) for driving theimage pickup device in accordance with the clock signal output from thefrequency modulation unit 1202, and other elements. An image signal fromthe image pickup device is converted into digital data of, for example,8 bits, and input to the shading correction circuit 1203 of the imageprocessing unit 1111, as an image data signal synchronizing with thefrequency-modulated clock signal.

[0119] The image data signal input to the image processing unit 1111 issubjected to pixel variation correction at the shading correctioncircuit 1203. In the magnification circuit 1204, a data thinning processis executed for a reduction copy, whereas a data interpolating processis executed for an enlargement copy. Next in the edge emphasis circuit1205, edges of an image are emphasized through second orderdifferentiation in a window of, for example, 5×5 pixels. Since the imagedata is luminance data, the image data is converted, for example, intodensity data in order to print it out at the laser unit 1109 (printer),by the gamma conversion circuit 1206 by using a table. The image dataconverted into density data is then input to the binarization processingunit 1207 whereat multi-value data is converted into binary data, forexample, by an ED (error diffusion) method. The binarized image data isinput to the synthesization circuit 1208.

[0120] The synthesization circuit 1208 selectively outputs either theimage data input from the binarization circuit 1207 or the image datainput from the image memory 1210 such as a DRAM and a hard disk via thememory control unit 1209 which controls the data read/write of the imagememory 1210. For example, if an image is to be rotated, it is rotated bycontrolling the read addresses of image data in the image memory 1210.The image data is input to the PWM circuit 1211 whereat it is convertedinto a signal corresponding to a radiation intensity of a laser beam sothat a signal having a pulse width corresponding to the image density isoutput to the laser unit 1109. A series of image processing descriedabove is performed synchronously with the frequency-modulated clocksignal.

[0121] Next, the details of the frequency modulation unit 1202 andfrequency modulation stop detection unit 1108 of the image processingapparatus of this embodiment will be given. Frequency modulation is oneof techniques for modulating in a narrow band a clock signal having afixed frequency to thereby reduce electromagnetic radiation of the fixedfrequency. For example, refer to U.S. Pat. No. 5,488,627 and U.S. Pat.No. 5,631,920.

[0122]FIG. 13 is a circuit diagram of the frequency modulation stopdetection unit 1108 of the image processing apparatus of thisembodiment. The frequency modulation stop detection unit 1108 has aphase comparator 1301 made of, for example, an EX-OR gate, a filter 1302made of, for example, a resistor and a capacitor, and a comparator 1303.The phase comparator 1301 compares an output of the quartz oscillator1202 with an output of the frequency modulation unit 1202. The filter1302 integrates an output of the phase comparator 1301. The comparator1303 compares an output of the filter 1302 with a reference voltage andoutputs a modulation stop detection signal to the I/O interface 1105depending upon the comparison result. FIG. 14A shows an output of thequartz oscillator 1201, FIG. 14B shows an output of the frequencymodulation unit 1202, FIG. 14C shows an output of the phase comparator1301, and FIG. 14D shows an output of the filter 1302.

[0123] Next, a frequency modulation stop operation to be executed by theimage processing apparatus constructed as above according to theembodiment of the invention will be described with reference to FIGS. 11to 14D and the flow chart of FIG. 15.

[0124] The clock signal (FIG. 14A) output from the quartz oscillator1201 and the clock signal (FIG. 14B) output from the frequencymodulation unit 1202 are input to the phase comparator 1301 of thefrequency modulation stop detection unit 1108. If these clock signalshave the waveforms shown in FIGS. 14A and 14B, an output signal of thephase comparator 1301 has the waveform shown in FIG. 14C. The outputsignal of the phase comparator 1301 is integrated by the filter 1302 andbecomes the signal shown in FIG. 14D. The voltage level of this signalshown in FIG. 14D is represented by V1. If the frequency modulation unit1202 is defective and the clock signal is not modulated, the phases ofthe clock signals input to the phase comparator 1301 are equal so thatV1 is 0 V.

[0125] The comparator 1303 compares the voltage level V1 with apredetermined reference voltage V_(REF) 1304, and outputs a high levelsignal if V_(REF)≧V1. If V_(REF) is set to a value very near to 0 V, themodulation stop detection signal takes the high level when the frequencymodulation unit 1202 becomes defective, and this high level signal issupplied to CPU 1101 via the I/O interface 1105.

[0126]FIG. 15 is a flow chart illustrating a control operation to beexecuted by the image processing apparatus when a frequency modulationstop is detected. When the high level modulation stop detection signalis supplied from the frequency modulation stop detection unit 1108 toCPU 1101 via the I/O interface 1105 (Step S501), CPU 1101 operates viathe I/O interface 1105 to display an alarm on an unrepresented display(e.g., liquid crystal display) on the operation panel 1106 (Step S502).CPU 1101 also backs up the error contents in RAM 1104 (Step S503) andthereafter turns off the relay circuit 1107 via the I/O interface 1105to turn off the power of the image processing apparatus.

[0127] As described so far, the image processing apparatus of thisembodiment has: the quartz oscillator 1201 for generating a clocksignal; frequency modulation unit 1202 for modulating the frequency ofthe clock signal output from the quartz oscillator 1201; imageprocessing unit 1111 for processing image data synchronously with theclock signal modulated by the frequency modulation unit 1202; frequencymodulation stop detection unit 1108 including the phase comparator 1301for comparing an output of the quartz oscillator 1201 with an output ofthe frequency modulation unit 1202, filter 1302 for integrating anoutput of the phase comparator 1301 and comparator 1303 for supplying amodulation stop detection signal to CPU 1101 when an output of thefilter 1302 is equal to or lower than V_(REF); and CPU 1101 whichoperates to display an alarm on a display on the operation panel 1106and turn off the relay circuit 1107 to turn off the power of the imageprocessing apparatus. The image processing apparatus therefore has thefollowing advantageous effects.

[0128] In the image processing apparatus having the above-describedstructure, the phase comparator 1301 of the frequency modulation stopdetection unit 1108 compares both outputs of the quartz oscillator 1201and frequency modulation unit 1202 and supplies the filter 1303 with anoutput signal in conformity with the comparison result. The filter 1302integrates an output of the phase comparator 1301 and outputs theintegrated signal to the comparator 1303. If the output of the filter1302 is equal to or lower than V_(REF), the comparator 1303 supplies CPU1101 with a modulation stop detection signal. Upon reception of themodulation stop detection signal, CPU 1101 operates to display an alarmon a display unit on the operation panel 1106 and turn off the relaycircuit to turn off the power of the image processing apparatus.

[0129] In this embodiment, therefore, the image processing apparatus canreduce electromagnetic radiation easily and with low cost. In addition,it is effective that electromagnetic noises can be prevented fromincreasing and adversely affecting other apparatuses, when the frequencymodulation function stops.

[0130] In the image processing apparatus of this embodiment, when thefrequency modulation stop detection unit 1108 detects a stop of themodulation function of the frequency modulation unit 1202, CPU 1101operates to display an alarm on a display on the operation panel 1106.The embodiment is not limited only thereto. For example, the imageprocessing unit may be provided with a sound output unit, and CPU 1101operates to produce alarm sounds from the sound output unit.

[0131]FIG. 16 is a block diagram showing the structure of an imageprocessing apparatus according to another embodiment. The imageprocessing apparatus of this embodiment has a CPU 2101, a bus drivecircuit/address decoder circuit 2102, a read-only memory (ROM) 2103, amain memory (RAM) 2104, an I/O interface 2105, an operation panel 2106,a relay circuit 2107, a modulation width monitoring unit 1108, a laserunit 2109, a charge-coupled device (CCD) unit 2110, an image processingunit 2111, and a video bus 2112.

[0132] The structure of each element will be detailed. CPU (centralprocessing unit) 2101 controls the entirety of the image processingapparatus, sequentially reads control programs from ROM 2103 to executethe processes illustrated in the flow chart of FIG. 20 and otherprocesses. The bus driver circuit/address decoder circuit 2102 connectsaddress and data buses of CPU 2101 to each load. ROM 2103 stores thereina control procedure (control programs) of the image processingapparatus. RAM (random access memory) 2104 is used as a storage area ofinput data or a working area of data. The I/O interface 2105 isconnected to: the operation panel 2106; devices (not shown) includingmotors, clutches, solenoids for driving a paper feed system, a transportsystem and an optical system, and paper detecting sensors for detectinga transported paper sheet; and to respective loads of the relay circuit2107, modulation width monitoring unit 2108 and laser unit 2109.

[0133] The operation panel 2106 includes various keys for entering databy an operator and a display unit such as a liquid crystal display andan LED for displaying the operation state and the like of the imageprocessing apparatus. The relay circuit 2107 turns on and off a power ofthe image processing circuit. The modulation width monitoring unit 2108monitors a modulation width of a modulated clock in the manner to bedescribed later. The CCD unit 2110 reads image data from an originalplaced on an original support and outputs it via the video bus 2112 tothe image processing unit 2111. The image processing unit 2111 performsimage processing to be described later for the image data output fromthe CCD unit 2110. The video bus 2112 connects the CCD unit 2110 to theimage processing unit 2111. The laser unit 2109 forms an image on asheet in accordance with image data supplied from the image processingunit 2111. The modulation width monitoring unit 2108 and CCD unit 2110will be detailed with reference to FIG. 17.

[0134]FIG. 17 is a circuit block diagram of the image forming apparatus,mainly the image processing unit 2111 thereof. The image processing unit2111 of the image processing apparatus of this embodiment has a shadingcorrection circuit 2203, a magnification circuit 2204, an edge emphasiscircuit 2205, a gamma conversion circuit 2206, a binarization processingunit 2207, a synthesization circuit 2208, a memory control unit 2209, animage memory 2210, and a pulse width modulation (PWM) circuit 2211. InFIG. 17, reference numeral 2201 represents a quartz oscillator, andreference numeral 2202 represents a frequency modulation unit.

[0135] The structure and operation of each element will be detailed. Thequartz oscillator 2201 outputs a clock signal having a fixed frequency.The frequency modulation unit 2202 is input with the clock signalsupplied from the quartz oscillator 2201 and outputs a clock signalwhose frequency was modulated. This frequency modulation will be laterdetailed. The modulation width monitoring unit 2108 is input with theclock signal from the quartz oscillator 2201 and the clock signal fromthe frequency modulation unit 2202, and outputs a modulation widthdetection signal when the modulation width of the input clock signalshifts from a reference value.

[0136] The CCD unit 2110 is constituted of a focussing lens (not shown)for focussing light reflected from an original, an image pickup device(not shown) such as a CCD, a CCD driver (not shown) for driving theimage pickup device in accordance with the clock signal output from thefrequency modulation unit 2202, and other elements. An image signal fromthe image pickup device is converted into digital data of, for example,8 bits, and input to the shading correction circuit 2203 of the imageprocessing unit 2111, as an image data signal synchronizing with thefrequency-modulated clock signal.

[0137] The image data signal input to the image processing unit 2111 issubjected to pixel variation correction at the shading correctioncircuit 2203. In the magnification circuit 2204, a data thinning processis executed for a reduction copy, whereas a data interpolating processis executed for an enlargement copy. Next in the edge emphasis circuit2205, edges of an image are emphasized through second orderdifferentiation in a window of, for example, 5×5 pixels. Since the imagedata is luminance data, the image data is converted, for example, intodensity data in order to print it out at the laser unit 2109 (printer),by the gamma conversion circuit 2206 by using a table. The image dataconverted into density data is then input to the binarization processingunit 2207 whereat multi-value data is converted into binary data, forexample, by an ED (error diffusion) method. The binarized image data isinput to the synthesization circuit 2208.

[0138] The synthesization circuit 2208 selectively outputs either theimage data input from the binarization circuit 1207 or the image datainput from the image memory 2210 such as a DRAM and a hard disk via thememory control unit 2209 which controls the data read/write of the imagememory 2210. For example, if an image is to be rotated, it is rotated bycontrolling the read addresses of image data in the image memory 2210.The image data is input to the PWM circuit 2211 whereat it is convertedinto a signal corresponding to a radiation intensity of a laser beam sothat a signal having a pulse width corresponding to the image density isoutput to the laser unit 2109. A series of image processing descriedabove is performed synchronously with the frequency-modulated clocksignal.

[0139] Next, the details of the frequency modulation unit 2202 andmodulation width monitoring unit 2108 of the image processing apparatusof this embodiment will be given. Frequency modulation is one oftechniques for modulating in a narrow band a clock signal having a fixedfrequency to thereby reduce electromagnetic radiation of the fixedfrequency. For example, refer to U.S. Pat. No. 5,488,627 and U.S. Pat.No. 5,631,920.

[0140]FIG. 18 is a circuit diagram of the modulation width monitoringunit 2108 of the image processing apparatus of this embodiment. Themodulation width monitoring unit 2108 has a phase comparator 2301 madeof, for example, an EX-OR gate, a filter 2302 made of, for example, aresistor and a capacitor, and comparators 2306 and 2307. The phasecomparator 2301 compares an output of the quartz oscillator 2202 with anoutput of the frequency modulation unit 2202. The filter 2302 integratesan output of the phase comparator 2301. The comparator 2306 compares anoutput of the filter 2302 with a lowest reference voltage and outputs amodulation width detection signal 1 to the I/O interface 2105 dependingupon the comparison result. The comparator 2307 compares an output ofthe filter 2302 with a highest reference voltage and outputs amodulation width detection signal 2 to the I/O interface 2105 dependingupon the comparison result. FIG. 19A shows an output of the quartzoscillator 2201, FIG. 19B shows an output of the frequency modulationunit 2202, FIG. 19C shows an output of the phase comparator 2301, andFIG. 19D shows an output of the filter 2302.

[0141] Next, a modulation width monitoring operation to be executed bythe image processing apparatus constructed as above according to theembodiment of the invention will be described with reference to FIGS. 16to 19D and the flow chart of FIG. 20.

[0142] The clock signal (FIG. 19A) output from the quartz oscillator2201 and the clock signal (FIG. 19B) output from the frequencymodulation unit 2202 are input to the phase comparator 2301 of themodulation width monitoring unit 2108. If these clock signals have thewaveforms shown in FIGS. 19A and 19B, an output signal of the phasecomparator 2301 has the waveform shown in FIG. 19C. The output signal ofthe phase comparator 2301 is integrated by the filter 2302 and becomesthe signal shown in FIG. 19D. The voltage level of this signal shown inFIG. 19D is represented by V1. If the modulation width becomes large,the potential level V1 becomes high, whereas if the modulation widthbecomes small, the potential level V1 becomes low.

[0143] A potential level 2304 corresponding to an allowable minimummodulation width of the image processing apparatus is represented byV_(REF1). and a potential level 2305 corresponding to an allowablemaximum modulation width of the image processing apparatus isrepresented by V_(REF2). The comparator 2306 compares the voltage levelV1 with V_(REF1), and the comparator 2307 compares the voltage level V1with V_(REF2). If V_(REF1)>V1 or V_(REF2)<V1, the modulation widthdetection signal 1 or 2 takes the high level and is supplied via the I/Ointerface 2105 to CPU 2101.

[0144]FIG. 20 is a flow chart illustrating a control operation to beexecuted by the image processing apparatus when a shift of themodulation width out of a reference range is detected. When the highlevel modulation width detection signal is supplied from the modulationwidth monitoring unit 2108 to CPU 2101 via the I/O interface 2105 (StepS1501), CPU 2101 operates via the I/O interface 2105 to display an alarmon an unrepresented display (e.g., liquid crystal display) on theoperation panel 2106 (Step S1502). CPU 2101 also backs up the errorcontents in RAM 2104 (Step S103) and thereafter turns off the relaycircuit 2107 via the I/O interface 2105 to turn off the power of theimage processing apparatus.

[0145] As described so far, the image processing apparatus of thisembodiment has: the quartz oscillator 2201 for generating a clocksignal; frequency modulation unit 2202 for modulating the frequency ofthe clock signal output from the quartz oscillator 2201; imageprocessing unit 2111 for processing image data synchronously with theclock signal modulated by the frequency modulation unit 2202; modulationwidth monitoring unit 2108 including the phase comparator 2301 forcomparing an output of the quartz oscillator 2201 with an output of thefrequency modulation unit 2202, filter 2302 for integrating an output ofthe phase comparator 2301, comparator 2306 for supplying the modulationwidth detection signal 1 to CPU 1101 when an output of the filter 2302is smaller than V_(REF1), and comparator 2307 for supplying themodulation width detection signal 2 to CPU 1101 when an output of thefilter 2302 is larger than V_(REF2); and CPU 2101 which operates todisplay an alarm on a display on the operation panel 2106 and turn offthe relay circuit 2107 to turn off the power of the image processingapparatus. The image processing apparatus therefore has the followingadvantageous effects.

[0146] In the image processing apparatus having the above-describedstructure, the phase comparator 2301 of the frequency modulation stopdetection unit 2108 compares both outputs of the quartz oscillator 2201and frequency modulation unit 2202 and supplies the filter 2303 with anoutput signal in conformity with the comparison result. The filter 2302integrates an output of the phase comparator 2301 and outputs theintegrated signal to the comparators 2306 and 2307. If the output of thefilter 2302 is lower than V_(REF1), the comparator 2306 supplies CPU2101 with the modulation width detection signal 1, whereas if the outputof the filter 2302 is higher than V_(REF2), the comparator 2307 suppliesCPU 2101 with the modulation width detection signal 2. Upon reception ofthe modulation width detection signal, CPU 2101 operates to display analarm on a display unit on the operation panel 2106 and turn off therelay circuit to turn off the power of the image processing apparatus.

[0147] In this embodiment, therefore, the image processing apparatus canreduce electromagnetic radiation easily and with low cost. In addition,it is effective that electromagnetic noises can be prevented fromincreasing and adversely affecting other apparatuses, when the frequencymodulation function stops.

[0148] In the image processing apparatus of this embodiment, when themodulation width monitoring unit 2108 detects a shift of the modulationwidth out of a reference range, CPU 2101 operates to display an alarm ona display on the operation panel 2106. The embodiment is not limitedonly thereto. For example, the image processing unit may be providedwith a sound output unit, and CPU 2101 operates to produce alarm soundsfrom the sound output unit.

[0149] The present invention may be applied to a system constituted of aplurality of apparatuses (e.g., a host computer, interface units, areader, a printer, and the like) or to a system constituted of a singleapparatus (e.g., a copier or a fax). The scope of the invention alsoincludes a system or apparatus whose computer (CPU or MPU) runs tooperate various devices connected thereto in accordance with softwareprogram codes supplied to the system or apparatus so as to realize thefunctions of the above embodiments.

[0150] In this case, the software program codes themselves realize theembodiment functions. Therefore, the program codes themselves and meansfor supplying such program codes to a computer, e.g., a storage mediumstoring such program codes, constitute the present invention.

[0151] The storage medium storing such program codes may be a floppydisk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, aCD-R, a magnetic tape, a non-volatile memory card, a ROM, and the like.

[0152] Obviously, such program codes are other types of embodiments ofthis invention, not only for the case wherein the embodiment functionsare realized by executing the program codes supplied to the computer butalso for the case wherein the embodiment functions are realized by theprogram codes used with an OS (operating system) on which the computerruns or with other various types of application software.

[0153] Furthermore, the scope of the invention also includes obviouslythe case wherein in accordance with the program codes stored in a memoryof a function expansion board or unit connected to the computer suppliedwith the program codes, a CPU or the like of the function board or unitexecutes part or the whole of the actual tasks for realizing theembodiment functions.

[0154] The invention has been described in connection with the abovepreferred embodiments. The invention is not limited only to the aboveembodiments, but various modification are possible without departingfrom the scope of the appended claims.

What is claimed is:
 1. An image processing apparatus comprising: amodulation circuit for frequency-modulating a clock signal; a memory forstoring image data; a write circuit for writing image data in saidmemory, synchronously with a first clock signal frequency-modulated bysaid modulation circuit; and a read circuit for reading image data fromsaid memory, synchronously with a second clock signal having a fixedfrequency.
 2. An image processing apparatus according to claim 1,further comprising an image processing circuit for processing an imagesignal synchronously with the frequency-modulated clock signal to formimage data.
 3. An image processing apparatus comprising: an imagereading unit for reading an original image; an image processing circuitfor subjecting an image signal read with said image reading unit to apredetermined image processing operation; a first clock generationcircuit for generating a first clock signal to be used for processingthe image signal; a frequency modulation circuit forfrequency-modulating the first clock signal output from said first clockgeneration circuit; a first timing signal generation circuit forgenerating a first image processing timing signal in accordance with thefirst clock signal frequency-modulated by said frequency modulationcircuit; an image data generation circuit for processing the imagesignal synchronously with the first image processing timing signalgenerated by said first timing signal generator circuit to generateimage data; a second clock generation circuit for generating a secondclock signal; a second timing signal generation circuit for generating asecond image processing timing signal in accordance with the secondclock signal output from said second clock generation circuit; a writecircuit for writing the image data generated by said image datageneration circuit in a memory, synchronously with the first timingsignal generated by said first timing signal generation circuit; a readcircuit for reading image data from-the memory, synchronously with thesecond timing signal generated by said second timing signal generationcircuit; and an image processing circuit for processing the image dataread from the memory.
 4. An image processing method comprising: amodulation step of frequency-modulating a clock signal; a write step ofwriting image data in a memory, synchronously with a first clock signalfrequency-modulated at said modulation step; and a read step of readingimage data from the memory, synchronously with a second clock signalhaving a fixed frequency.
 5. An image processing method according toclaim 4, further comprising an image processing step of processing animage signal synchronously with the frequency-modulated clock signal toform image data.
 6. An image processing method comprising: an imagereading step of reading an original image; an image processing step ofsubjecting an image signal read at said image reading step to apredetermined image processing operation; a first clock generation stepof generating a first clock signal to be used for processing the imagesignal; a frequency modulation step of frequency-modulating the firstclock signal generated at said first clock generation step; a firsttiming signal generation step of generating a first image processingtiming signal in accordance with the first clock signalfrequency-modulated at said frequency modulation step; an image datageneration step of processing the image signal synchronously with thefirst image processing timing signal generated at said first timingsignal generator step to generate image data; a second clock generationstep of generating a second clock signal; a second timing signalgeneration step of generating a second image processing timing signal inaccordance with the second clock signal generated at said second clockgeneration step; a write step of writing the image data generated atsaid image data generation step in a memory, synchronously with thefirst timing signal generated at said first timing signal generationstep; a read step of reading image data from the memory, synchronouslywith the second timing signal generated at said second timing signalgeneration step; and an image processing step of processing the imagedata read from the memory.
 7. A storage medium storing a program forrealizing an image processing method, the method comprising: amodulation step of frequency-modulating a clock signal; a write step ofwriting image data in a memory, synchronously with a first clock signalfrequency-modulated at said modulation step; and a read step of readingimage data from the memory, synchronously with a second clock signalhaving a fixed frequency.
 8. A storage medium according to claim 7,wherein the method further comprises an image processing step ofprocessing an image signal synchronously with the frequency-modulatedclock signal to form image data.
 9. A storage medium storing a programfor realizing an image processing method, the method comprising: animage reading step of reading an original image; an image processingstep of subjecting an image signal read at said image reading step to apredetermined image processing operation; a first clock generation stepof generating a first clock signal to be used for processing the imagesignal; a frequency modulation step of frequency-modulating the firstclock signal generated at said first clock generation step; a firsttiming signal generation step of generating a first image processingtiming signal in accordance with the first clock signalfrequency-modulated at said frequency modulation step; an image datageneration step of processing the image signal synchronously with thefirst image processing timing signal generated at said first timingsignal generator step to generate image data; a second clock generationstep of generating a second clock signal; a second timing signalgeneration step of generating a second image processing timing signal inaccordance with the second clock signal generated at said second clockgeneration step; a write step of writing the image data generated atsaid image data generation step in a memory, synchronously with thefirst timing signal generated at said first timing signal generationstep; a read step of reading image data from the memory, synchronouslywith the second timing signal generated at said second timing signalgeneration step; and an image processing step of processing the imagedata read from the memory.
 10. An image processing apparatus comprising:a clock signal generation circuit for generating a clock signal; afrequency modulation circuit for modulating a frequency of a generatedclock signal; and a detection circuit for detecting an operation stateof said frequency modulation circuit.
 11. An image processing apparatusaccording to claim 10, wherein said detection circuit detects theoperation state of said frequency modulation circuit in accordance witha comparison result between an output of said clock signal generationcircuit and an output of said frequency modulation circuit.
 12. An imageprocessing apparatus according to claim 11, wherein said detectioncircuit detects a stop of a modulation function of said frequencymodulation circuit when the comparison result between an output of saidclock signal generation circuit and an output of said frequencymodulation circuit indicates a value equal to or lower than a referencevalue.
 13. An image processing apparatus according to claim 12, furthercomprising a control circuit for turning off a power of the imageprocessing apparatus when said detection circuit detects a stop of themodulation function of said frequency modulation circuit.
 14. An imageprocessing apparatus according to claim 12, further comprising an alarmcircuit for issuing an alarm when said detection circuit detects a stopof the modulation function of said frequency modulation circuit.
 15. Animage processing apparatus according to claim 10, wherein said detectioncircuit detects a modulation width of said frequency modulation circuit.16. An image processing apparatus according to claim 11, wherein saiddetection circuit detects a modulation width of the clock signal inaccordance with a comparison result between an output of said clocksignal generation circuit and an output of said frequency modulationcircuit.
 17. An image processing apparatus according to claim 16,wherein said detection circuit detects a shift of the modulation widthout of a reference range when the comparison result between an output ofsaid clock signal generation circuit and an output of said frequencymodulation circuit is smaller than a minimum reference value or largerthan a maximum reference value.
 18. An image processing apparatusaccording to claim 17, further comprising a control circuit for turningoff a power of the image processing apparatus when said detectioncircuit detects that the modulation width of said frequency modulationcircuit shifts out of the reference range.
 19. An image processingapparatus according to claim 17, further comprising an alarm circuit forissuing an alarm when said detection circuit detects that the modulationwidth of said frequency modulation circuit shifts out of the referencerange.
 20. An image processing method comprising: a clock signalgeneration step of generating a clock signal; a frequency modulationstep of modulating a frequency of a generated clock signal; and adetection step of detecting an operation state of frequency modulation.21. An image processing method according to claim 20, wherein saiddetection step detects the operation state of frequency modulation inaccordance with a comparison result between a clock signal generated atsaid clock signal generation step and a clock signal modulated at saidfrequency modulation step.
 22. An image processing method according toclaim 21, wherein said detection step detects a stop of a frequencymodulation function when the comparison result between the clock signalgenerated at said clock signal generation step and the clock signalmodulated at said frequency modulation step takes a value equal to orlower than a reference value.
 23. An image processing method accordingto claim 22, wherein said detection step includes a control step ofturning off a power of an image processing apparatus when said detectionstep detects a stop of the frequency modulation function.
 24. An imageprocessing method according to claim 22, wherein said detection includesan alarm step of issuing an alarm when said detection step detects astop of the frequency modulation function.
 25. An image processingmethod according to claim 20, wherein said detection step detects amodulation width at said frequency modulation step.
 26. An imageprocessing method according to claim 21, wherein said detection stepdetects a modulation width of the clock signal in accordance with acomparison result between a clock signal generated at said clockgenerating step and a clock signal modulated at said frequencymodulation step.
 27. An image processing method according to claim 26,wherein said detection step detects a shift of the modulation width outof a reference range when the comparison result between the clock signalgenerated at said clock generating step and the clock signal modulatedat said frequency modulation step is smaller than a minimum referencevalue or larger than a maximum reference value.
 28. An image processingmethod according to claim 27, wherein said detection step includes acontrol step of turning off a power of an image processing apparatuswhen said detection step detects that the modulation width at saidfrequency modulation step shifts out of the reference range.
 29. Animage processing method according to claim 27, wherein said detectionstep includes an alarm step of issuing an alarm when said detection stepdetects that the modulation width at said frequency modulation stepshifts out of the reference range.
 30. A storage medium storing aprogram for realizing an image processing method, the method comprising:a clock signal generation step of generating a clock signal; a frequencymodulation step of modulating a frequency of a generated clock signal;and a detection step of detecting an operation state of frequencymodulation.
 31. A storage medium according to claim 30, wherein saiddetection step detects the operation state of frequency modulation inaccordance with a comparison result between a clock signal generated atsaid clock signal generation step and a clock signal modulated at saidfrequency modulation step.
 32. A storage medium according to claim 31,wherein said detection step detects a stop of a frequency modulationfunction when the comparison result between the clock signal generatedat said clock signal generation step and the clock signal modulated atsaid frequency modulation step takes a value equal to or lower than areference value.
 33. A storage medium according to claim 32, whereinsaid detection step includes a control step of turning off a power of animage processing apparatus when said detection step detects a stop ofthe frequency modulation function.
 34. A storage medium according toclaim 32, wherein said detection step includes an alarm step of issuingan alarm when said detection step detects a stop of the frequencymodulation function.
 35. A storage medium according to claim 30, whereinsaid detection step detects a modulation width at said frequencymodulation step.
 36. A storage medium according to claim 31, whereinsaid detection step detects a modulation width of the clock signal inaccordance with a comparison result between a clock signal generated atsaid clock generating step and a clock signal modulated at saidfrequency modulation step.
 37. A storage medium according to claim 36,wherein said detection step detects a shift of the modulation width outof a reference range when the comparison result between the clock signalgenerated at said clock generating step and the clock signal modulatedat said frequency modulation step is smaller than a minimum referencevalue or larger than a maximum reference value.
 38. A storage mediumaccording to claim 37, wherein said detection step includes a controlstep of turning off a power of an image processing apparatus when saiddetection step detects that the modulation width at said frequencymodulation step shifts out of the reference range.
 39. A storage mediumaccording to claim 37, wherein said detection step includes an alarmstep of issuing an alarm when said detection step detects that themodulation width at said frequency modulation step shifts out of thereference range.